[private_island]

Thank you for all the great comments and feedback so far. Note that Betsy uses an Altera Cyclone 10 LP (not GX). This is a low cost, general purpose FPGA. The Ethernet PHY interface is RGMII, which utilizes 5 bits of parallel DDR + clock instead of SERDES.

As many of you probably know, SERDES and specialized PCS/CDR blocks will get you well past 1 GigE, but 1 GigE for RGMII is challenging with 125 MHz single-ended traces.

The project compiles super fast with the Quartus tools and Signal Tap enabled with several active configurations. Quartus bundles the Questa simulator, so there is a great environment for simulation.

Regarding Certus-NX, this indeed would also be a great choice. Lattice does a very nice job exposing their I/O primitives, and I believe the RGMII DDR could be instantiated directly in the I/O cells for both input and output (this could definitely be accomplished with the earlier ECP5). We actively design with Certus-NX, and a future Betsy revision using it is very possible.