This reminded me reading (ages ago) about Altera’s HardCopy [1]: a “process that takes a working FPGA design implemented in one of Altera’s high-end FPGAs (such as Stratix II) and gives you a functionally- and footprint-equivalent ASIC at a fraction of the unit cost.”
Did a bit of Googling and realised it seems to be still alive in the form of Intel’s eASIC! [2].