[bgnn]

One thing to realize is the lifetime is a statistical thing.

I design chips in modern tech nodes (currently using 2nm). What we get feom the fab is a statistical model of device failure modes. Aging is one of them. When transistors gradually age they get slower sue to increased threshold voltage. This eventually causes failure at a point where timing is tight. When will it happen varies greatly sue to initial conditions, exact conditions the chip was in(temp, vdd, number of on-off cycles, even the workload). After an agong failure the chip will still work if the clock freq is reduced. There are aging monitors on-chip sometimes which try to catch it early and scale down the clock.

There are catastrophic failures too, like gate insulator breakdown, electromigration or mechanical failures of IO interconnect. The last one is orders of magnitude more likely than anything else these days.