[fernirello]

Clarification question, having read OP yet having missed some fine details: I presume you mean that software could set some CIA-II register to keep the NMI line to the CPU down indefinitely. Since what triggers the handling of an NMI is the transition from high to low, that means no other handler (in particular the Freeze Frame's) would get executed. And one'd also need to redirect the NMI vector, which normally is in Kernel ROM, to a dummy handler consisting of an RTI or little more. Correct?

[michalpleban]

Yes, that's absolutely correct

[fernirello]

Thank you!

[michalpleban]

An addendum: the way you would program the CIA registers to pull the NMI low would most likely be to set up one of its timers on a very short count period (IIRC four system clock cycles is the lowest the chip can do) and make it generate the underflow interrupt. The chip holds the interrupt line low until you acknowledge the interrupt by reading the interrupt source register. If you never get to read it, the interrupt line stays low forever.