[MegaDeKay]

I checked out his post on Reddit [0]. OP (cyao12) wrote a CPU in Verilog at the age of 13 and is now only 16. Mind. Blown.

  cyao12: I'm going to try and put the old cpu I made in verilog when I was 13 on it! The sdram is okay, the traces are short enough that the distance difference doesn't matter :D

  Collez_boi: You made a freaking CPU in Verilog when you were 13?! That's crazy.

  cyao12: Yeaaah, but tbh the design wasnt really good lol. Im 16 now so Im quite happy about my progress

[0] https://www.reddit.com/r/FPGA/comments/1kwxvk8/ive_made_my_f...