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by NooneAtAll3 381 days ago
ha, I'm not the only one to think "so what's all the risc5 gmp fuss was about, if carry flag is slow anyway?"
1 comments

Right.

Even at that time in 2021 I argued that serialising through a carry flag is limiting on wide machines, but there was very little RISC-V hardware available at the time and also GMP was not yet ported to RISC-V.

That has changed a bit now, and almost two months ago I tried the GMP project's own gmpbench on a few RISC-V boards.

I found that when comparing similar µarch at similar clock speed, in dual-issue in-order SiFive's U74 is very comparable to Arm's A53, and in small 3-wide OoO SiFive's P550 is significantly better than Arm's A72.

And that's not even using the kind of technique discussed in this post, but the full multi-instruction carry flag emulation criticised by Granlund.

https://www.reddit.com/r/RISCV/comments/1jsnbdr/gnu_mp_bignu...

It's going to be very interesting when the 8-wide OoO RISC-V cores come out, probably starting with Tenstorrent's Ascalon core which they expect to tape out in Q3 and they have said they want to get into as many hands as possible to accelerate RISC-V development, including in laptops, not only in servers or the like.