|
|
|
|
|
|
by oasisaimlessly
405 days ago
|
|
|
See e.g. Migen [1], a Python HDL. TL;DR: The hardware modules you're generating are represented as first-class objects that can be constructed from a DSL embedded within Python or explicitly from a list of primitives. [1]: https://m-labs.hk/gateware/migen/ |
|
|