[tails4e]

SystemVerilog is a much better language than verilog. You can get pretty strong typed behaviour now, if you use the language parts that allow that. It's like C, if you use it poorly/the 'verilog way' it's got some serious footguns, but you can use it quite safely if you use the more modern features.

That said, I'm all for better languages, of they really are better and as expressive

[IshKebab]

It's better than Verilog but it's still awful. If you thought C had footguns....

[tails4e]

What do you find thats so awful? Once you understand the main footguns and how to avoid them, it's overall very solid.

[wirybeige]

To add, even before SV we've had VHDL which is also strongly typed and has other nice features. But I do still like using SV more than VHDL :3. I'm not wholly convinced of these languages that have been popping up so far.

[thezoq2]

Spade author here :) Coming from a functional programming adjacent background, the VHDL type system leaves a lot to be desired. Not supporting types with generics means you can't encode things like a genral purpose ready/valid stream. When you have those, you can start using methods to compose those streams which becomes even more powerful when you add higher order functions which allow you to transform the content of the stream without worrying about the stream details.