[bobmcnamara]

There's definitely a trade-off between things that seem relatively simple to ISA but can really complicate the pipeline.

Xtensa pays for it with crippled 64-bit performance, which has a lot of downstream impacts. Ex: division by a constant is also slower. Most compilers don't even bother fast pathing 64-bit division by a constant.

I was surprised to find Apple kept ADC/ADCS in aarch64. Maybe this ends up being one of those things that's less useful or potentially a bottleneck depending on the specific implementation. Edit: backwards compatibility probably.

The fact that a few cores have bolted it on to RISC-V makes me think I must not be alone in missing it.