[pjc50]

> rise of LLMs lowering the barrier of entry of software even lower

Getting to your first wafer costs something like $250k and upwards of fab costs, depending on what process you're using. Hence much of chip design effort is already spent on verification, it's probably over 50% by now. This is the exact opposite of vibes because mistakes are expensive.

Businesswise it's quite tough B2B sales because you're selling into other people's product development pipelines. They need to trust you because you can sink their project, way over and above the cost of the actual parts.

Edit: I cannot emphasise enough how much more conservative the culture is in chip design and EE more broadly. It belongs to a world not just before "vibe coding" but before "web 2.0". It's full of weird closed source very expensive tooling, and is built on a graveyard of expensive mistakes. You've got to get the product 100% right on the first go.

Well, maybe the second go, production silicon is usually "B" rev. But that's it. Economics dictate you then need to be able to sell that run for a few years before replacing it with an upgraded product line.

[StormChaser_5]

The rule of thumb I use for chip design is that verification takes at least 2/3s of development. Sometimes more. 50% would be nice but I think is optimistic

[docfort]

Verification is indeed the majority of the time spent. Unlike programming, Verilog and VHDL and higher level things like Chisel aren’t executed serially by the hardware they describe like a von Neumann machine. Hello World for a chip isn’t designing the circuit, or simulating the circuit, or synthesizing the circuit to some set of physical primitives. No, it’s proving that the circuit will behave correctly under a bunch of different conditions. The less commoditized the product, the more important it is to know the real PDK, the real standard cell performance, what to really trust from the foundry, etc. Most of the algorithms to assist in this process are proprietary and locked behind NDAs. The open source tools are decades behind the commercial ones in both speed and correctness, despite heavy investment from companies like Google.

And so my point: the place where people best know how to make chips competitively in a cutthroat industry is NOT in schools, but in private companies that have signed all the NDAs. The information is literally locked away, unable to diffuse into the open where universities efficiently operate. Professors cannot teach what they don’t know or cannot legally share.

Chip design is a journeyman industry. Building fault-tolerant, fast, power-efficient, correct, debuggable, and manufacturable designs is table stakes. Because if not, there are already a ton of chip varieties available. Don’t reinvent the wheel because the intersection of logic, supply chain logistics, circuit design, large scale multi objective optimization, chemistry, physics, materials science, and mathematical verification is unforgiving.