F = Field
P = Programmable
G = Gate <---- important
A = Array
You aren't "programming", you're "wiring gates together". In other words, you can build custom hardware to solve a problem without using a generic CPU (or GPU) to do it. FPGAs are implemented as a fabric of LUTs (Look-up Tables) which take 4- or 6- (or more) inputs and produce an output. That allows Boolean algebra functions to be processed. The tools you use (Vivado / ISE / YoSys / etc.) take a your intended design, written in a HDL (Hardware Design Language) such as Verilog or VHDL, and turn it into a configuration file which is injected into the FPGA, causing it to be configured to into the hardware you want (if you've done it right). FPGAs are a stepping stone between generic hardware such as a CPU or GPU and a custom ASIC. They win when you can express the problem in specialized hardware much better than writing code to do something on a CPU/GPU. Parallelization is the key to many FPGA designs. Also, you don't have to spend >$1MM on a mask set to go have an ASIC fabricated by TSMC, etc.
Given the density of the PDF, I saw AMD and AI in the title and assumed the scientific community was trying to get AMD GPUs to work. This makes more sense.
You aren't "programming", you're "wiring gates together". In other words, you can build custom hardware to solve a problem without using a generic CPU (or GPU) to do it. FPGAs are implemented as a fabric of LUTs (Look-up Tables) which take 4- or 6- (or more) inputs and produce an output. That allows Boolean algebra functions to be processed. The tools you use (Vivado / ISE / YoSys / etc.) take a your intended design, written in a HDL (Hardware Design Language) such as Verilog or VHDL, and turn it into a configuration file which is injected into the FPGA, causing it to be configured to into the hardware you want (if you've done it right). FPGAs are a stepping stone between generic hardware such as a CPU or GPU and a custom ASIC. They win when you can express the problem in specialized hardware much better than writing code to do something on a CPU/GPU. Parallelization is the key to many FPGA designs. Also, you don't have to spend >$1MM on a mask set to go have an ASIC fabricated by TSMC, etc.