[aap_]

I have a bunch of KA10 verilog that worked on a DE10-nano in the past, but it's been quite a while and i think i have a bunch of uncommitted stuff lying around as well. The verilog is based on the original schematics and I successfully ran LISP and Spacewar on it. Unfortunately simulating peripherals is always a pain, so the project currently lies dormant. But i'd like to pick it up again at some point. I just really need to rethink my approach how to do this, qsys was maybe not the greatest way to wire up the system.

https://github.com/aap/fpdpga/tree/master/ka10

[rahen]

It’s exciting to hear that you’ve successfully run LISP and Spacewar on it, especially since the Verilog is based on the original schematics. That makes the PiDP-10 an actual KA-10 CPU, which is a big deal for authenticity.

I completely understand the difficulty with simulating peripherals. Perhaps the FPGA could focus on implementing the CPU, leaving the peripherals to a SIMH backend using a hybrid approach. A slightly longer PCB with space for both a DE10-nano and an RPi 0 might work out well.

Have you considered opening a discussion on VCFED or Google Groups to gather more ideas and see what others think? I’m sure many people would be excited to follow and contribute to that progress.

I'm looking forward to seeing how this develops.

[aap_]

I hadn't connected it to the pidp-10 panel yet actually, my stuff is older than that. but eventually i would like to. the approach i went with was to put some of the peripherals on the linux side of things but have the controller logic on the FPGA. it's all a bit fiddly with FPGAs...