[ChrisGammell]

I'm generally in the "never trust the autorouter" camp (and by extension "never trust the bevy of AI tools entering the space"), but it's undeniable there are some big opportunities in the eCAD space to speed up some aspects of layout. I'm probably more likely to use co-creation tools, rather than full auto tools, simply because I rely heavily on iteration. Many times when starting a design my placements aren't set and that has a huge impact on routing. I didn't see on your page whether placement was part of your algorithm. I already rely on tools like push and shove and occasionally auto complete.

I'm always curious about people entering the space though. It is a small market, IMO. The tools are fractured, the existing players are lumbering behemoths, and the users are cranky zealots (you will have to pry KiCad out of my cold dead hands). I noted the step about the AR being written in JavaScript, which I have no real opinion on, but I'm curious about plans to plug into ecosystems (CAD vendors, OS tools) or try and draw people into another new ecosystem.

[seveibar]

We will absolutely be supporting KiCad! Placement is something we have big plans for but I think it’s important to have a really fast, cache-friendly autorouter as a foundation (if you are cache friendly, moving components and trying different layouts is much much faster)

Javascript is fairly portable now with many runtimes (some even quite small such as QuickJS or Proffor), so I anticipate people will be able to run locally and build their own ginormous cache :)

I think everyone should be concerned about lockin and fragmenting ecosystems in EDA, but tscircuit and our autorouter are MIT-permissive technology (very rare in EDA) so we play nice (interoperable) with everyone.

[micw]

> We will absolutely be supporting KiCad

I wonder why there's no standard API for autorouting so that a particular EDA must be supported. I'd love to see autorouter as a standardized HTTP endpoint so that I can run one locally or even buy Autorouter-As-A-Service. E.g. I'd happily pay for TopoR¹ as a service for some projects while others are fine with classic rouing.

¹) https://de.wikipedia.org/wiki/TopoR

[seveibar]

Software innovation in EDA seems pretty slow and is more IP-sensitive, so there hasn't been a huge proliferation of cloud services. We're trying to bring some up some standards that make EDA more web-friendly, like the Circuit JSON[1] format and the Simple Route JSON format[2], but it'll still be years before the tools support web-first standards (kind of reminds me of png vs webp)

[1] https://github.com/tscircuit/circuit-json

[2] https://docs.tscircuit.com/advanced/simple-route-json

[buescher]

The de facto standard external autorouter workflow is through specctra files.

[micw]

At lease easyeda has support for http based autorouter endpoints. They seem to wrap a version of freerouting in this protocol

[_fizz_buzz_]

How are you planning to support kicad? Would it be using kicad's new IPC API? In principle it should be possible to create javascript bindings for the new protobuf interface.

[seveibar]

We are looking hard at the IPC interface or doing a plugin, but we will also support “uploading” kicad_sch/kicad_pcb to a browser (local-first, so not actually uploading)

[cushychicken]

Hey - take a look at my other reply to u/ChrisGammell - I have some input on your project you might find useful that I don’t feel like retyping lol

[buescher]

Years ago the long-gone and unlamented OrCAD Layout had a spreadsheet view of your nets that was a slightly better than good-enough interface for setting constraints for autorouting. Once you got your footprints, placement, constraints, and hand-routed nets locked down, you could iterate very quickly.

It's nice to see anyone at all working on PCB autorouters, which have been pretty stagnant since Cadence bought SPECCTRA in the nineties. The guys who wrote SPECCTRA went to the VLSI world iirc and never came back - I guess that's where all the fame and fortune is. Probably was a patent minefield for a while there too; might still be. Autoplacement was an utterly intractable problem back then, still seems to be, and it's probably ripe for a generative AI approach - a good generative AI first pass at parts placement could be a net time saver. The biggest problem would be convincing the cranks that you can be good even if you can't be perfect.

I'm sort of puzzled by the kids out there trying to do schematics-as-code. On the one hand, I would love to see that work as a backend format - especially where folks like the jitx guys seem to be making a lot of progress in encoding appnote and datasheet-level design rules into parts models. Reading every datasheet in the detail needed for commercial designs is more work than people expect, and so is getting junior engineers on board with the process. So any automation there is beneficial. The problem is that the approaches all seem rooted in this idea of schematics as data entry for layout, a kind of source code, rather than as design documentation with a carefully evolved visual language that needs to be accessible to people who won't have an EDA suite installed on their computer. I guess people who learned from puzzling out schematics in the Adafruit/Sparkfun/Shenzhen style with explicit wiring minimized might not understand the value of a good schematic.

The other thing is leaning too far into thinking-by-analogy and trying to make PCB-level design like VLSI design. I don't think it's entirely impossible - if we had better tools for DRC and validation, component-level design would look more like VLSI design. But the design space is so different, with such loose coupling between design, EDA/CAM/simulation, validation, fabricators, assemblers, component vendors, regulators/certifiers, and so on that just getting one corner of it really right would be a major accomplishment.

[Joel_Mckay]

For any benefit the auto-router adds, it usually ends up costing a project later...

In general, impedance controlled UHF design work with domain specific simulation tools is the modern workflow. Thus, one manually does the critical tracks first, island-pours, and finally power interconnects.

KiCad is slightly better than nothing for layout, and trying to make it into yet another half-baked simulation tool seemed silly. =3

[cushychicken]

I wish the Kicad team had sunk all the time they put into simulation support (which I rarely use, in or out of kicad) into a proper constraint system instead.

If I need to sim, I’ll just use LTspice or TI TINA - I.e. the simulation ecosystem that includes the part model I need, with no wrangling to get that spice model to play nicely in some other spice toolchain.

[Joel_Mckay]

Micro-cap 12 is still available, was made free, and runs in Wine64 just fine.

https://web.archive.org/web/20230214034946/http://www.spectr...

For learning, the current LTSpice models and QUCS VNA profiled device imported simulation data are reasonable tools as well.

I used KiCad all the time for personal projects, and it has recently already addressed the major issues people found annoying:

1. unstable library version dependency management

2. complex design collaboration over traditional versioning tools like git (still an upstream feature last I checked, but should be available soon.)

3. freezing the specific KiCad and library path structure versions across a project, as assuming every design has a single workstation workflow is a contradictory goal

KiCad is better than most current EDA software, but that is mostly a sad reflection on the traditional tools available. =3

[cushychicken]

Where can I learn more about this Kicad git workflow? I’ve heard a lot about it but I’d like to see it for myself.

[Joel_Mckay]

Did you mean this page?

https://forum.kicad.info/t/tutorial-how-to-enable-git-in-kic...

Or the plugin and content manager under the tools menu for the git-gui module...

YMMV =3

[_fizz_buzz_]

I love the ngspice integration in kicad it has gotten really good since kicad 7 or 8.

[cushychicken]

The tools are fractured, the existing players are lumbering behemoths, and the users are cranky zealots (you will have to pry KiCad out of my cold dead hands).

These last five years have been absolutely incredible to watch in Kicad’s development. Last two releases have added the two major things that Kicad didn’t have that professional CAD tools did:

* database support

* outjob features

Beyond that, it’s really just a matter of adoption and end user preference of how to put these features to work. (Databases tend to come with a lot of internal corporate bureaucracy around organizing data than anything else.)

But, for the topic at hand: don’t you think Kicad is already moving sort of in the direction you talk about, as far as workflow to speed up layout is concerned?

Best example I can think of is the “trace autocomplete” feature in I think 7.0. Hit hotkey (I think it’s F in pcbnew) and the trace will be laid for the track currently being placed. Combine this with the “route from other end of track” (hotkey E), this is a blazing productivity boost, especially when you’re working across two different ball out grids.

Version 9 enabled buses/multiple tracks to be draggable, meaning this whole system could go even faster still.

Many times when starting a design my placements aren't set and that has a huge impact on routing.

Honestly, I’d trust an autorouter to complete a good chunk of my designs if I can get to a placement I’m satisfied with, and I can give the autorouter some constraints on where to route. For example: did a board last year using an NXP iMX8MP with an eMMC. The peripheral ballout on the processor matches the eMMC ballout really nicely - was just a matter of lining the chips up and drawing the lines. An autorouter could have done in seconds what it took me ~10 minutes if it had known to keep everything in the data bus on the top layer.

I think that’s a success criteria autorouter projects suffer from: they don’t consider their autorouter “done” unless their router can do _everything_ on a board. As a working EE, I don’t actually want that. I want an autorouter that can work with me to do a satisfactory job on a little chunk of the design at a time, give me some time to review it for correctness, then move on to the next chunk.

That would be killer. Especially if you could give constraints beyond layers: I.e “keep all nets with names D0-7 on layer one and three, and match their length to 5mm of one another. Use D0 as the net length reference.” If you can do that, then boom: you’ve solved DRAM length tuning. Huge range of design complexity now within reach of the unwashed masses.

OP - if I can find some time to show you what I mean, I’d be more than happy to give you a demo of what I’m talking about.

[seveibar]

Hey cushychicken! Would love to see what you’re working on and thanks for explaining (seveibar at tscircuit dot com is my email if you want to set something up!)

I do think humans need to be in the loop on autorouters, but I also think autorouters should be very fast and decent. In web design we progressively add constraints (via CSS) to tweak the output of the visual design and see the result instantly, I believe this same workflow is possible for PCB design (and will favor those good at specifying constraints!)

[cushychicken]

Thanks for the reply. I’ll get in touch via email in the next few days.

I don’t think the goals of “human in the loop” and “fast and decent” are mutually exclusive, or really even at odds with each other.

I just think that most autorouters I’ve tried seem to have been written by CS people who thought PCB layout was an interesting problem to solve - without a particularly deep understanding of what working EEs care about in terms of how you route the board.

Case in point: plenty of autorouters seem to work on the paradigm of “all tracks routed? Great. I’m done.” Never mind that everything is two layers of spaghetti: no ground plane, no power planes, no regard for SI or EMC compliance. In other words: pure hell to test and certify.

Not trying to be crotchety EE by saying this - I can give a good example of what I mean in real time. I also feel like I’m a bit of the exception in the EE community in that I think this is a solvable problem. I just don’t think many CS people have really bothered to consult any real working EEs about their workflows and the downstream portion of test and certification.

[rjsw]

I once had to do bringup on an autorouted prototype PCB. The traces between the CPU and DRAM looped three times round the board.