[adastra22]

None of that is needed. You're talking about surface events per square meter (roughly) and we're talking about a device with total dimensions smaller than a single TSMC 2nm transistor. The cross section is so small that the chance of it being hit over the lifetime of the product is ignorable. There are way bigger operational risks to worry about.

[defrost]

I provided real data about gamma events.

You're welcome.

I trust you can do the math scaling from events per 42 litre volume to the volume in question here.

The altitude and air density factor in, any LEO applications have an increased risk, etc.

> The cross section is so small that the chance of it being hit over the lifetime of the product is ignorable.

Always a possibility under consideration: https://en.wikipedia.org/wiki/Qantas_Flight_72#Potential_tri...

[adastra22]

> I provided real data about gamma events.

At an irrelevant scale. The cross sectional area of these devices will be 18 - 20 orders of magnitude smaller.

> Always a possibility under consideration...

We're talking about the cross section of a macro-scale (visible with the naked eye) chip vs. a cluster of a few dozen atoms. Certainly you can understand the difference of scale? Cosmic ray induced bit flips are extremely infrequent events at the datacenter scale.

What's the frequency at which a single, specific transistor will be struck? Not that a bit flip occurs somewhere in a large datacenter, but the chance of just a specific transistor being hit. Now reduce that 100-fold. That's the base rate we're talking about.