[Ellipsis753]

Is this saying that intel will support _only_ 512 instructions? (And not 256).

Or that it'll support _both_ 256 and 512 instructions going forwards (and stop doing the nonsense where some cores support 512 and others don't?)

[adrian_b]

AVX10 will continue to support 512-bit instructions, 256-bit instructions, 128-bit instructions and scalar instructions (FP32 & FP64), exactly like the current AMD and Intel CPUs with AVX-512 support.

So none of the current instructions will be removed.

The previous plan of Intel was that in consumer CPUs the 512-bit instructions shall be removed, keeping only 256-bit instructions, 128-bit instructions and scalar instructions (FP32 & FP64).

Nevertheless, the most ancient versions of AVX-512 had only 512-bit instructions and scalar instructions.

The 256-bit instructions and 128-bit instructions have been added in Skylake Server, as a workaround for the bad power management of Intel at that time, which forced huge drops in clock frequency for long times when using wide instructions.

On modern CPUs there is no need to use 256-bit or 128-bit instructions. You gain nothing with them. AVX10 instructions have masks, so you can process any arbitrary length with a 512-bit instruction, in the case of loop prologues or epilogues.

The use of 512-bit instructions simplifies many optimized programs, because one instruction processes one cache line.

[snvzz]

Zen4 made it very difficult for Intel to make 512 a premium feature.

[phkahler]

Zen 5 beats Arrow Lake without AVX512. For workloads that use it you then get another huge performance jump with Zen 5, but Arrow Lake doesn't even have the instructions.

[fweimer]

One clear reason to use 128-bit instructions: naturally aligned 128-bit loads and stores are only atomic if encoded as EVEX.128 (or VEX.128 etc.).

The default auto-vectorization tuning for current Intel server CPUs using 256-bit registers, which is perhaps another counterexample.

[janwas]

The auto-vectorization (which I anyway would not rely on) default setting also sounds like a workaround for the SKX issue.

For atomic, I'm curious how you make use of that?

[chad1n]

It will support both, but considering the previous experiences with avx 512 on intel, I wouldn't that excited