[Aurornis]

> It’s space-inefficient as half of the CPUs are shutdown

In practice is doesn't matter very much for a design like this. The size is already limited to a certain minimum to provide enough perimeter area to provide wire bonding area for all of the pins, so they can fill up the middle with whatever they want.

[DrNosferatu]

They should have filled it with more SRAM instead - 520KB is far too little.

[Tharre]

What difference would the extra 16KiB or whatever instead of the 2 RISC-V cores make? If 520KB is far too little for you, you're likely better off adding a 8 MiB PSRAM chip.

[DrNosferatu]

Just 16KB? Couldn’t a lot more be fitted?

PSRAM has huge latency.

[timschmidt]

SRAM takes up a tremendous amount of space compared to logic. Usually at least six transistors per bit, plus passives, plus management logic.

[Lerc]

SRAM is big in gate count. typically 6 transistors per bit.

The i386, a 32 bit chip already dragging around a couple of generations of legacy architecture came in at 275,000. I would imagine the Hazard3 would be quite a bit more efficient in transistor usage due to architecture.

16K is 16384(bytes) *8(bits per byte) *6(transistors per bit) = 786, 432

[DrNosferatu]

It was the first CPU on my desk! 80386SX 25MHz.

(this one, only 32bit internally)

[DrNosferatu]

Thanks for the explanations - was not aware.

…vertically stack a slab of SRAM above or beneath the CPU die, does come to mind ;)

[murderfs]

This is way too expensive for something like a microcontroller. AMD calls this 3D V-Cache and uses it on their top end SKUs.

[DrNosferatu]

But doesn't the ESP32-S3-WROOM have some large on-chip RAM?

For the Pico, say, something in the line of the approach taken by many smartphone SoCs that package memory and processor together.

[pjc50]

I believe there's already a separate Flash die in the same package. Probably not possible to add yet another die for DRAM.

(for various chemistry reasons, it's much more efficient to manufacture Flash, DRAM, and regular logic on separate wafers with different processing)

[DrNosferatu]

Wouldn't the massive increase in capabilities from adding 8MB-16MB of closely-integrated, fast RAM far outweigh the modest price increase for many applications that are currently memory-constrained on the Pico?