[Karrot_Kream]

Pruning excess gates will be interesting. I know this sort of thing generally works with reachability analysis, but I'm curious in practice how thorny this will be. Moreover I'm curious how "interpretable" the resulting circuits will be.

Either way this research is fantastic. What a result.

[vessenes]

For sure. I guess you could run static analysis on the gates to determine what "hits" and what doesn't -- I'm not a chip designer, but I know the tools are super sophisticated, and these are, ultimately, very small circuits.

I know that some early AI physics-enabled designs utilized "weird" analog features, but at small geometries especially, and in real life, everything is analog anyway. If these are gate-level, I guess the interpretability questions will be literally on assessing logic. There's so many paths to dig in here, it's super interesting.