| It's not a backdoor. Caravel is fully open source. You can audit it. There is no ROM (except for a project ID), just 1.5KB of RAM, a CPU, a few peripherals and (most importantly) the pad ring. Caravel is a (questionable) attempt to lower the barriers of entry to silicon design, both the cost and required skill. It lowers cost, because every single chip on the MPW is the same size, and can be tested with a common interface. They can test the RISC-V core and pad ring to get a good indication of the die quality (theoretically they can upload user-submitted code to test the actual design, but I don't think have implemented that), and only package up the highest quality dies that are most likely to work. It lowers required skill, because the user doesn't have to worry about getting the pad ring right. When they receive their chip, they are guaranteed to have a working RISC-V core, and caravel provides a bunch of logic analyser probes you can hook directly into your design to debug why it's not working. It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate. The Caravel harness makes it very clear what the target market for the eFabless product is. It's not for end products, you only get a few chips. It's for people, especially hobbyists to learn how to do silicon design. (Though, IMO it's nowhere near cheap enough for that target market.) If you want an actual end product, you should be contracting either with eFabless or directly with Skywater for a full wafer with a custom pad ring. |
in theory only.
caravel had hold time violations and the pin configuration mostly didn’t work for the first 5 or 6 sponsored OpenMPW shuttles.