[nsteel]

I'm sorry I don't have that. It's partly supply and demand and looking at what the early adopters (Apple, these days) need. And then there's interplay with specs and related roadmaps (i.e. nobody develops their HBM PHY IP until the spec is mature enough). HPC traditionally requires specialist memory IP (e.g. CAM) and more SRAM varieties, so that comes later. Serdes also comes later since it pushes the process limits, both analogue and digital, and also is tied into ethernet standards. You might find public marketing material from Synopsys/Cadence?