[thunderbird120]

If it were that simple fabs wouldn't offer a standard cell libraries in both high performance and high density varieties. TSMC continues to provide both for their 2nm process. A tradeoff between power efficiency and raw performance continues to exist.

[zozbot234]

A standard cell can be a critical performance bottleneck as part of a chip, so it makes sense to offer "high performance" cell designs that can help unblock these where appropriate. But chip cooling operates on the chip as a whole, and there you gain nothing by picking a "higher raw performance" design.

[thunderbird120]

If that were totally true you would expect to see more or less uniform ratios of HP/HD cells mixes across different product types, but that's very much not the case. Dennard scaling may be dying but it's not dead yet. You can still sacrifice efficiency to gain performance. It's not zero sum.

[zozbot234]

What product types do you have in mind exactly? Even big server chips now use a huge fraction of their area for power-sipping "efficiency core" designs that wouldn't be out of place in a mobile chip. Power is king.

[monocasa]

Those efficiency cores would put a full core from just a few years ago to shame, and data center chips have always contained a majority niche focused on throughput and perf/watt over latency. That's nearly always been focused on somewhere closer to the 45° part of the scurve than more on the top.

[tarnith]

AMD Zen5?