[sakras]

I was going to buy one of these until I realized it didn't have vector extensions. I expected something with "Performance" and "Premier" in the name to have them. I think some sort of SIMD capability is table stakes for a lot of workloads these days, so I'm disappointed that there doesn't seem to be a CPU on the market that supports them. I've heard that the vector extensions being stateful makes them particularly hard to implement, which makes me wonder if there needs to be some sort of simpler-to-implement version which mirrors more traditional SIMDs like AVX2 and Neon.

[adgjlsfhk1]

The SiFive P670 has vector support, and apparently dev boards using it are expected by end of year.

[sakras]

Oh that's exciting, I will be on the lookout for that!

[brucehoult]

> I was going to buy one of these until I realized it didn't have vector extensions

A statement like this pretty much disqualifies your opinions. Why would you expect it to have vector extensions? No one has ever claimed it does, the P550 materials clearly specify the ISA, and the RVA22 spec it implements does not require it.

However it is the fastest RISC-V CPU you can buy today, on a per core basis, by a factor of two, for all those many workloads that don't benefit from SIMD. For example general use as a desktop PC, compiling code etc.

It may well be eclipsed by another factor of two by this time next year (and by something with vector), but that's the rapid pace of progress in RISC-V.

If you need to develop non-vector code on RISC-V this year then this -- or the Mil-V Megrez for half the price and 30% high clock speed -- is the machine to have.

If you don't need RISC-V this year then ... go buy an x86. Or an Orion O6 (which I will also be getting)

> I think some sort of SIMD capability is table stakes for a lot of workloads these days, so I'm disappointed that there doesn't seem to be a CPU on the market that supports them

Some workloads, yes. Not all.

As for what is on the market, the CanMV-K230 with RVV 1.0 shipped in November 2023, and a wide variety of boards and laptops with the SpacemiT K1/M1 SoCs with octa core CPU with 256 bit RVV 1.0 shipped in the 2nd half of 2024, including the Banana Pi BPI-F3, Milk-V Jupiter, Sipeed Lichee Pi 3A, Deep Computing DC-Roma II laptop, MuseBook. Various of these have been reviewed by everyone from Jeff Geerling to Christopher Barnatt to Hackaday.

As for "some sort of SIMD" that's been available in RISC-V since the Allwinner D1 chip shipped in mid 2021, first on the AWOL Nezha EVB, later on things such as the Lichee RV and MangoPi MQ-Pro. These days the same C906 CPU (1 GHz, 128 bit vectors) is available in other SoCs for as little as $3-$5 in the 1 GHz Milk-V Duo with 64 MB RAM (runs a full Linux kernel), up to the $9.90 Duo S with 512 MB RAM.

There are also various boards with the 1.85 GHz quad core C910 TH1520 SoC, such as the Lichee Pi 4A and Milk-V Meles.

Not to mention the 64 core 2.0 GHz 128 GB RAM 64 MB L3 cache 32 PCIe lanes Milk-V Pioneer.

[sakras]

> A statement like this pretty much disqualifies your opinions

This is needlessly aggressive. I specialize in writing SIMD code. That is my job. I am very eager to get my hands on a RVV chip so that I can play with a new SIMD ISA. So obviously a non-SIMD chip is useless to me.

> Why would you expect it to have vector extensions?

Because it has "Performance" in the name. I double-checked the ISA and saw that it did not have V, and was disappointed.

> If you don't need RISC-V this year then

Why would anybody _need_ RISC-V? RISC-V is exciting because it has the possibility of giving the end user higher performance per dollar. Until it does that, it will relegated to enthusiasts who just like playing with new ISAs.

[brucehoult]

> This is needlessly aggressive.

I apologise.

> I specialize in writing SIMD code. That is my job. I am very eager to get my hands on a RVV chip

The P550 core was announced in June 2021, 2 1/2 years ago. It was stated at the time that it doesn't have RVV.

The X270, announced the same day, is a dual-issue in-order core that DOES have RVV.

https://www.sifive.com/press/sifive-performance-p550-core-se...

I've also been eagerly waiting for RVV 1.0 hardware (and programmed RVV 0.7.1 hardware in the meantime, as a very close proxy ... and the C910 has a quite high performance implementation as an OoO core with dual vector pipelines) so I follow the news, mostly on Reddit's /r/riscv.

Boards with in-order cores implementing RVV 1.0 have been shipping since November 2023.

Those of us who follow the news have been eagerly awaiting the SG2380 SoC and Milk-V Oasis (and other) boards with it. Sixteen 2.5 GHz OoO SiFive P670 cores with RVV, plus 8 SiFive X280 cores with RVV as an NPU.

This was originally announced in October 2023 with predicted delivery in September 2024 (which tbh was never believable, and I expressed that at the time), then January 2025, and then late 2025 (which probably should have been the target in the first place), and now it may be cancelled because of US government sanctions.

> Because it has "Performance" in the name.

That comes from marketers, not engineers.

But it is indeed the fastest RISC-V available today, per core, on real-world scalar code, by a factor of 2. (The C910 is close on code that runs from L1 cache, maybe L2).

> Why would anybody _need_ RISC-V?

At the moment because they want to develop software to be ready when the machines competitive with the top end of Arm and/or x86 do arrive. Or if the current performance and price level already meets their needs e.g. Samsung with their future line of TVs (prototype already demonstrated at a show) using the P470 core. Samsung has had a team porting and optimising their Tizen OS and Microsoft's CoreCLR JIT for about two years now. No doubt similar activity is happening at LG, who have also announced switching to RISC-V.

> has the possibility of giving the end user higher performance per dollar. Until it does that

We are already more than half way from ratification of the base ISA in mid 2019 to that date. Probably 2/3 of the way. The SoCs that will do that are already on the drawing boards. Time is short and there is much to do.

[drmpeg]

The SpacemiT K1 SoC implements RVV1.0. It can be found on the Banana Pi BPI-F3 and the Milk-V Jupiter boards.

[adgjlsfhk1]

Unfortunately the K1 is horribly slow. It's an in order processor, doesn't have L3 cache and has pretty slow floating point multiplies. It's an OK dev board for riscv-V, but it is closer to Raspberry pi 3 than the P550 which is a lot closer to a Pi 4 for general performance.

[drmpeg]

Yes, it was very disappointing. I was hoping the 8 cores would give a speedup for compiling code, but no dice. On a large Linux build, the BPI-F3 with make -j8 takes exactly the same time as a make -j4 on the VisionFive 2.

[brucehoult]

Nothing except the Pioneer (and now this and the Milk-v P550) has L3 cache.

BPI-F3 (etc) has only 512 MB of L2 cache for each cluster of 4 cores, vs 2 MB on the VisionFive 2 (etc), and I think this is the biggest issue. Similarly the TH1520 only has 1 MB of L2.

The Pioneer has the same 1 MB of L2 per four cores, but backs this up with 4 MB of L3, and when you're running single-threaded (or just a few) that CPU also has access to the other 60 MB of L3 cache on the chip at still much better than DRAM latency and bandwidth. It's very nice-perofrming machine if you can afford it -- though the P550 should make a better desktop machine. I'll know in a week or two when my Megrez arrives...