[audunw]

But in a large SRAM, most of the gates are not switching, at any given time. The cells are mostly just sitting there holding their data.

And if cooling it lets you shrink the SRAMs that’s also going to let you reduce the capacitance, so switching power will also be reduced. I’m sure a design optimised for low temp will do some clever stuff with clock hating as well.

The problem here is that you generally put SRAM on the same die, or at least package, as the processors. And those do switch many of their gates.

So you’d probably have to do this in a case where you want a lot of fast RAM in a different box, with some really fast optical interconnect to your processing cores.

[bsder]

The sense lines, however, are switching--as is the clock. Just because the RAM cells are sitting there doing nothing doesn't mean that everything else in the RAM is also idle.

Also, take a look at the Apple M3 chip, for example. Note how much of the die size isn't RAM.