[hn3er1q]

If anyone is interested in adder taxonomy and why one might select one architecture over another in VLSI I can highly recommend this slide deck.

https://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect17.pdf

In particular slides 36 and 37

[kens]

I especially like slide 36, the "time cube" diagram of adder architectures.