[variaga]

>do chiplets have better power gating than monolithic?

like a lot of stuff, the full answer is "it depends", but mostly - no. Chiplets and monolithic ICs get about the same power gating quality/efficiency (whatever your metric is).

>I’d assume a whole chiplet could have its power cut completely.

You _could_ do this - put a chiplet on an isolated power plane in the package and then cut the power to the entire chiplet. But that is IMO rare because (a) you've just moved the problem somewhere else - the power gates now need to appear on your board, not on the PCB - and (b) frequently you don't want to completely cut the power to a whole chiplet..

For instance you may want to keep some data resident in internal memory as the (power/time) cost of re-writing that data after a "full" power down may exceed the extra power saved between the full/partial power down. You'll end up doing a pretty tedious analysis of how long does it take to initialize the chiplet and how long is it likely to be powered down vs. the different power consumption in the different modes.

Anyway, on chip power gating is very good - you really can turn the power off 100% in the gated region - at the cost of extra silicon area for an isolation band around the gated region and level shift/isolation cells for all the I/O into/out-of the gated region - all of which you also have to do in the "power down the whole chiplet" approach.