The guts of an FPGA are a lot of D-flip-flops in chains, that shift in the bitstream, and then send control signals to LUTs, switching fabric, etc. What I propose is to remove most of the switching fabric, so that every cell is identical, and add latching to every cell's output, to eliminate timing (especially race conditions) as a concern.
Every cell only has short connections to neighbors, so the capacitance of high speed lines that cause such grief in large VLSI designs is mostly removed (you do still need to clock those latches, so those would take some good drive signal).
The guts of an FPGA are a lot of D-flip-flops in chains, that shift in the bitstream, and then send control signals to LUTs, switching fabric, etc. What I propose is to remove most of the switching fabric, so that every cell is identical, and add latching to every cell's output, to eliminate timing (especially race conditions) as a concern.
Every cell only has short connections to neighbors, so the capacitance of high speed lines that cause such grief in large VLSI designs is mostly removed (you do still need to clock those latches, so those would take some good drive signal).