Hacker News new | ask | show | jobs
by ryao 550 days ago
An uncached random memory access is around 100 cycles.
1 comments

100 cycles would be very low. Many systems have more than 100 ns!
You are correct. I used the wrong unit:

https://jsmemtest.chipsandcheese.com/latencydata

We can say around 100ns, although likely somewhat more.