[XzAeRosho]

It says so in the article itself:

>Excluding interconnects, the SRAM and CCD should add up to less than 20µm thick. To accommodate such small and fragile components, AMD has added a bulky layer of dummy silicon at the top and the bottom for structural integrity.

[MoreMoore]

The article doesn't answer questions like whether this is unusual, if other CPUs historically have had a lot of dummy silicon, whether this is expensive or how it impacts the cost of production or how it affects the complexity of production itself. It's what I'd expect from modern journalism, but not really what I expect from good journalism.

[Tuna-Fish]

Traditionally, it's not needed.

The way nearly every CPU starting right from 4004 has worked is that they take a silicon wafer that's about half a mm thick, do a lot of photolithography, etching, deposition and other stuff to build the cpu on the top side of it, flip it upside down and bond it to the package. Only the very surface layer of the silicon is active in any way, the rest of the bulk is used for structural support and spreading heat laterally (necessary because heat is not evenly distributed at all, the hot spots get very hot). Power and signals come from the package below, heat is dissipated to the top.

The x3d chips change this, because in it there are two silicon dies bonded together, right on top of each other. The lower one of these dies gets through-silicon vias built into it, so it can provide power and signals for the top one. In prior generations, there was a normal CPU on the bottom, and they put the cache chip on top. For Zen5, they reversed that.

A complication is that apparently the process they use to bond them requires the top chip to be thinned. This means it's structurally weak and that heat spreads worse laterally, which would be bad for top clocks. So they bond another, thicker piece of silicon on top of it.

[rob74]

Well, that was kinda my point:

- traditional: bottom - actual IC; top - "dummy silicon" (part of the same chip).

- new: bottom - thin IC 1; middle - thin IC 2; top - "dummy silicon" (separate chip)

[knowitnone]

"requires the top chip to be thinned" and then "bond a thicker piece of silicon on top of it." That doesn't seem very efficient to me but I'm sure they know what they are doing.

[hnuser123456]

Yes, people have found you can sand the die down by ~0.3mm on a 9900k if you are that desperate to improve temps by 2-3 degrees C: https://www.youtube.com/watch?v=O1ed_rBRb7Q&t=525s

[rcxdude]

Yeah. I think that other CPUs do also have a large chunk of 'dummy' silicon, except it's just the wafer that it's manufactured on the surface of, instead of a seperate part that's added after the wafer is ground down to allow for the connections through the back.

[tecleandor]

I'd say it's load bearing silicon. Like, literally.