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by gsmecher
585 days ago
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These experiments are always unique, and each is interesting in its own way. Can you comment on the use of asynchronous code rather than generators? For example, here's a throw-away example of a clock using generators and a syntax that's otherwise similar to yours: from more_itertools import take
def drv_clock():
while True:
yield "1b1"
yield "1b0"
for x in take(10, drv_clock()):
print(x)
I have written signal flow graphs (including feedback) using a generator-style approach, intended to prototype datapaths that are then manually translated into RTL. It's different, but not completely different. |
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But control threads like a clock/reset aren't the main idea. Look at the example RISC V core for the design style we're attempting (https://github.com/cjdrake/seqlogic/tree/main/tests/riscv/co...). No async/await or yields anywhere. It's described in a structural way, and a couple layers of Python hide the details.