[snvzz]

Hmm, I had missed that. Perhaps the C line (e.g. C6) would be more suited.

Espressif CEO expressed commitment to RISC-V (now already years ago) and they've stopped releasing new chips with tensilica ISA.

As the ecosystem, toolchains and such aren't comparable to that of RISC-V and this gap will only widen, they really shouldn't be selected for new designs.

[auguzanellato]

C line isn’t also very comparable: single (C-series) vs dual core (S3), and S3 has USB-OTG capabilities whereas C6 only has USB-JTAG.

Tensilica ESPs aren’t formally in NRND stage as of right now, for some usages they’re still the only choice, even if RISC-V is clearly the path forward.