[leecb]

I wonder how much of this increase is solely enabled by TSMC process upgrades, either through higher clock speeds or increased number of transistors per core? It's kind of interesting that every iteration of the M series has corresponded to a change of TSMC process.

M1: 16 billion transistors at 3.2 GHz on TSMC N5

M2: 20 billion transistors at 3.7 GHz on TSMC N5P

M3: 25 billion transistors at 4.05 GHz on TSMC N3B

M4: 28 billion transistors at ?? GHz on TSMC N3E

[dagmx]

N3E is slightly less efficient than N3B though, it just has higher yields.

[Fluorescence]

Do both efficiency and yield play a part in the final off the shelf performance?

e.g. does higher yield mean you get more product in higher bins? I imagine we need to judge a process by the distribution across bins not just a max efficiency or a total yield.

[dagmx]

Perhaps if this was intel or AMD with many binned SKUs, but Apple has very minimal SKUs and less binning wouldn’t account for as large a single core jump