[ggm]

Wafer scale integration has been a thing since wafers. Yet, I almost never read of anyone taking it the full distance to a product. I don't know if it turns out the yield per die per wafer or the associated technology problems were the glitch, but it feels like a good idea which never quite makes it out the door.

[desertrider12]

They don't give yield numbers but this says that they get acceptable yields by putting extra cores on the silicon and then routing around the defective ones. https://cerebras.ai/blog/wafer-scale-processors-the-time-has...

[ggm]

I found this bit interesting: They worked with TSMC to ensure the off-die areas used for test and other foundry purposes have been more clearly circumscribed so they can use the blanks between the chips for the inter-chip connects. The distances are kept short and they can avoid a lot of encode/decode logic costs associated with how people used to do this:

"The cross scribe line wiring has been developed by Cerebras in partnership with TSMC. TSMC allowed us to use the scribe lines for tens of thousands of wires. We were also allowed to create certain keep-out zones with no TSCM test structures where we could embed Cerebras technology. The short wires (inter-die spacing is less than a millimeter) enable ultra-high bandwidth with low latency. The wire pitch is also comparable to on-die, so we can run the inter-die wires at the same clock as the normal wires, with no expensive serialization/deserialization. The overheads and performance of this homogeneous communication are far more attractive than those of multi-chip systems that involve communication through package boundaries, transceivers, connecters or cables, and communication software interfaces."

[mastax]

I believe I’ve heard them say they have 100% yield. They haven’t made very many yet though, on the order of 100.