[tonetegeatinst]

I'd bet that making a chip the size of the waver has the benefit on not losing any silicon to dicing the wafer up like a desktop or GPU chips coming from a wafer. Major downside is you need to either have a massive x and Y exposure size or break the wafer into smaller exposures which means your still needing to focus on alignment between the steps, and if a defect can't be corrected then is that wafer just scrap?

[throwup238]

They fuse off sections of the wafer with defects just like other manufacturers do in monolithic CPUs (as opposed to chiplets like AMD).