Won’t that negatively impact the life expectancy of the device? FRAM is rated for trillions of reads and, if the SRAM is frequently read, a trillion reads isn’t that much.
>100 trillion reads per location over 30 years still means you gotta read locations at over 100 kHz 24/7. Not good enough for main memory, sufficient even for frequently accessed configuration values.
Yes. It'd be a problem for running code directly from it - it'd be better to cache it to DRAM so that all reads would come from DRAM and only writes would make it to FE-RAM.
IIRC, it was a common trick with 286 and 386 PCs, because BIOS ROMs were 8-bit wide and shadowing the BIOS in RAM made it much faster.