[sirn]

Some N100 do have In-Band ECC (which uses the same data lane as regular memory channel, so less usable memory space/effective memory bandwidth), such as the Beelink S12 Pro box (DDR4) and is recognized by EDAC subsystem on Linux.

    [    8.485808] [    T703] caller igen6_probe+0x138/0x780 [igen6_edac] mapping multiple BARs
    [    8.487601] [    T703] EDAC MC0: Giving out device to module igen6_edac controller Intel_client_SoC MC#0: DEV 0000:00:00.0 (INTERRUPT)
    [    8.487625] [     T67] EDAC igen6 MC0: HANDLING IBECC MEMORY ERROR
    [    8.487626] [     T67] EDAC igen6 MC0: ADDR 0x7fffffffe0
    [    8.487664] [    T703] EDAC igen6: v2.5.1

[cromka]

DDR5 has in-band ECC by default on all platforms, though.

[sirn]

DDR5 doesn't have an In-Band ECC. What they have is On-Die ECC, and is not visible to the memory controller (i.e. error information won't be reported by EDAC), and only corrects 1-bit when they're stored/retrieved, where Side-Band ECC (regular ECC) and In-Band ECC can correct 1-bit and detect 2-bits, and can also correct/detect memory corruption during transit.

[cromka]

Ohhh right, right, I had them mixed up! Thanks for the clarification.