[foft]

There are a few improvements that could still be useful:

i) FPGA on a newer process so it can clock higher. For faster 68k in the Amiga core and pentium 1 equivalent speeds in the x86 core.

ii) Faster ARM chip and better ARM-FPGA fabric, opening up hybrid emulation. Currently the ARM-FPGA layer is a real bottleneck and also the ARM core is a little slow.

iii) More spare IO to allow per-system custom io boards.

iv) Built in IO/memory board so they can fit in a nicely designed case rather than the current eyesore.

[crtified]

Some of those wishes may be addressed by the DE25 line, which is under investigation as a possible next-gen direction for MiSTer.

As discussed in https://www.youtube.com/watch?v=1Z0l9cLO0jA

[snvzz]

>ii) Faster ARM chip and better ARM-FPGA fabric, opening up hybrid emulation. Currently the ARM-FPGA layer is a real bottleneck and also the ARM core is a little slow.

I'd hope for replacement with the open standard RISC-V instead, as used in many of the newer FPGA families.