[chaboud]

I think that’s fair. It was, in effect, a cache and DMA target. A similar scheme was present in the Cell, where the SPE’s had 256KB of embedded SRAM that really needed to be addressed via DMA to not drag performance to the ground. For low-level optimization junkies, it was an absolute playground of traps and gotchas.

Edit: if memory serves, SPE DMA list bandwidth was just north of 200GB/s. Good times.