| It's already succeeded in the embedded world, displacing not only a lot of use of Arm, but also pretty much killing off all other custom ISAs that some company engineer invented in order to not have to go through the hassle of licensing a core. All the major FPGA companies now offer a fully-supported RISC-V soft core as well as cores with their proprietary ISAs, and several FPGA companies already offer chips with RISC-V hard cores. In ASICs Synopsys now offers ARC-V and Cadence has some deals in place. In applications processors chips about to come out in the next 12 months, such as this XiangShan and the SG2380, are getting up into the performance level of 10 year old Zen and Core i5 etc, which is still a perfectly fine performance level for many people and uses. Linux has been available for RISC-V for many years, a number of distros have 2nd tier support for RISC-V, probably moving to 1st tier soon. Android is working towards 1st class support for RISC-V, with the desired ISA extensions, fast enough hardware, and full software porting looking to converge into competitive products around 2026-2027. Arm is NOT a "common ISA". It is proprietary and support can be arbitrarily removed at any time. Since 2023, Arm's highest performance CPU cores have dropped support for the 32 bit ISA(s) even for user programs. That's orphaning an almost 40 year history of 32 bit Arm software, restricting it to being used only on legacy CPUs which will rapidly have much less performance than newer high end CPUs. At the same time, the low end Arm microcontroller family remains 32 bit only. And the 32 bit and 64 bit ISAs are totally different to each other. RISC-V vendors on the other hand are happy to license you a 64 bit core with Cortex-M0 or Cortex-M3 size and features. These are often valuable as a control processor in a bigger chip with 64 bit applications processors and >32 bit address space. In RISC-V the 32 bit and 64 bit ISAs are almost identical and it's very cheap and easy to support 32 bit code on a 64 bit CPU -- the RISC-V spec fully supports this, though demand is low as there is not yet a lot of legacy 32 bit RISC-V code. Most current RISC-V CPU cores don't support this, though for example the THead C908 does. |