[zellyn]

This is fantastic. I once dreamed of making a generic interface card that could be programmed at will, using, say, a raspberry pi. However, a look through the timing diagrams in Sather shows surprisingly tiny latencies between the address and r/w signals hitting the bus, and the memory value needing to be presented. I concluded that an fpga would probably be required. Always fun when you can wait a few years and someone smarter than you builds the thing you imagined!

[edanuff]

Project co-creator here - This was something I'd wanted to do since I first started playing with FPGAs 20 years ago but the idea was resurrected during the pandemic. It's definitely easier with an FPGA but there are other projects that interface an ESP32 or RP2040 to the Apple II bus. The FPGA approach allows you to architect your logic in ways that are much closer aligned to the original hardware design and in many cases, you can directly translate Sather's logic diagrams to Verilog code. BTW, Sather's book has recently been reissued: https://www.callapple.org/books-3/understanding-the-apple-ii...