[edanuff]

Project co-creator here - that's actually the V1 board, the V2 board is here https://github.com/a2fpga/a2fpga_core/blob/main/boards/a2n20... and uses a slightly larger CPLD (complex programmable logic device) which is what's used to map and level shift the 5V signals from the Apple II bus to the 3.3V pins on the FPGA module. We use the Sipeed Tang Nano 20K FPGA module for the FPGA. Using a pre-built module like this is a great accelerator in this type of project because a lot of the more complicated things to get right, like the power supplies or the length of the traces for the HDMI connector, are done for you.

[robinsonb5]

Very cool project - I'd be all over this if I was lucky enough to own an Apple II!

(I think there's a typo in the credits section of the github Readme: you have alanswx listed as Alex Steremberg instead of Alan?)

[edanuff]

Yup, definitely Alan not Alex! Alan has been the person who has brought a lot of attention to the Apple II core in the Mister FPGA platform.

[classichasclass]

Quick question: my ROM03 IIgs has a Transwarp GS, SCSI card-hard disk and GGlabs 8MB RAM card. Think this would work with that configuration, or would it likely have conflicts?

[edanuff]

I have the exact same setup except for the SCSI card and it works with that. The issue will be if the SCSI card is in one of the slots that has been virtualized on the FPGA (4 and 7 by default), in which case there will be address range conflicts. For example, if the SCSI card is in slot 7, then it will conflict with the SuperSprite functionality which uses the address range for Slot 7. There is a "No-Sprite" version of the firmware which disables the SuperSprite or you can move the SCSI card to Slot 3 and put the A2FPGA in Slot 7. ROM03 GS units have the necessary address line signals that the A2FPGA needs on all the slots whereas previous models of the GS only had those on Slot 3.

[classichasclass]

I think it's in 6 (or was it 3?), but I'll verify. Thanks for the info!