| > Not sure what you mean by "peephole heuristic optimizations" Post-emit or within-emit stage optimization where a sequence of instructions is replaced with a more efficient shorter variant. Think replacing pairs of ldr and str with ldp and stp, changing ldr and increment with ldr with post-index addressing mode, replacing address calculation before atomic load with atomic load with addressing mode (I think it was in ARMv8.3-a?). The "heuristic" here might be possibly related to additional analysis when doing such optimizations. For example, previously mentioned ldr, ldr -> ldp (or stp) optimization is not always a win. During work on .NET 9, there was a change[0] that improved load and store reordering to make it more likely that simple consecutive loads and stores are merged on ARM64. However, this change caused regressions in various hot paths because, for example, previously matched ldr w0, [addr], ldr w1, [addr+4] -> modify w0 -> str w0, [addr] pair got replaced with ldp w0, w1, [add] -> modify w0, str w0 [addr]. Turns out this kind of merging defeated store forwarding on Firestorm (and newer) as well as other ARM cores. The regression was subsequently fixed[1], but I think the parent comment author may have had scenarios like these in mind. [0]: https://github.com/dotnet/runtime/pull/92768 [1]: https://github.com/dotnet/runtime/pull/105695 |