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by rscott2049
682 days ago
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Almost correct - the third implementation does generate the clock, but it isn't necessary to drive the clock directly from the system clock, as there are m/n clock dividers available. I use a 300 MHz system clock, and divide down to 50 MHz which works well. (I've also addressed a few other shortcomings of this library, but am not done yet...) Haven't looked at the 10 MHz half duplex mode, though. |
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Also, are there any other approaches that might be better and would offer 100meg or even gigabit links with the RP2350? Thanks!