| Either performance or stability/reliability. Or even both. At higher frequencies (during a frequency boost phase for example) signal quality in the digital signals degrades, because the "stable 1" or "stable 0" plateau is shortened and the "maybe 1 or 0" phase in between stays the same. So a signal that is supposed to be as rectangular as possible gets smushed down towards a sinus, and then smushed even further towards lower amplitudes. One measure against this is of course better (faster) transistors, such that the "maybe" phase is shorter, but that only works by replacing the hardware. The other measure, which you can do during runtime, is to increase the signal amplitude by increasing the voltage. Then even a degraded signal close to the transistors' maximum switching frequency gets over the "stable 1" and "stable 0" thresholds fast enough. With a lower supply voltage you can thus not clock the CPU as high as before which is important in boost phases during high load. Which would decrease peak performance in standard desktop and server workloads, and decrease overall performance in compute-intensive workloads. Or if you still clock it as high as before, signal quality will be lessened, increasing the probability of bit errors, lessening system stability and reliability of results. Which direction intel will pick for this firmware upgrade, degraded-performance, degraded-stability or degraded-both, I don't know, I guess we'll see. |