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by dailykoder
689 days ago
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>This is why it's probably a good idea to work with a HDL instead of just trying to wing it. During my CE studies I got hooked heavily on FPGAs and HDLs, but the amount of times I actually ran into a timing problem, which only occured on hardware, because of these delays, can be counted on one hand. Playing around with this crap since about 2018. The worst one was where I got clock domain crossing wrong while trying to get DDR3 RAM working for my master thesis. It worked flawless in simulation. Took me weeks to find the wrong status signal Yes, they can be a serious problem. Yes, you should know about it. But no, it's not necessary |
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