[musicale]

Whichever one you like - they are basically equivalent in terms of what they can do. Verilog is more like C while VHDL is more like Ada.

We're in a golden age of youtube videos teaching you the basics of Verilog/VHDL, digital design, computer architecture, FPGAs, CPU implementation, etc. Starting in simulation (like verilator and gtkwave) is a great idea because 1) it's free 2) you get easy visibility into the low-level behavior of your design and 3) simulation is an important part of hardware design, testing, and debugging.

Besides HDLs (which are great) you can also use block design tools; for example, hneemann's Digital (which was influenced/inspired by Logisim) looks like it could be a nice learning, development, and simulation tool - and it also exports to Verilog and VHDL. There are several web-based environments as well.

I've also recently run into some other HDLs which look interesting, such as Migen, which is used in the LiteX SoC framework and implements an HDL as a Python library. (It also has successors which I have not used.)