[pkkim]

The Antmicro team are doing good work with making Verilator support SystemVerilog / UVM tests but from what I understand it's not complete yet.

I've also heard from various people that although Verilator is generally fast, it tends to choke on compiling sufficiently large designs, whereas the Cadence and Synopsys offerings eventually get it done.

Still, Verilator is an awesome piece of software. Maybe the biggest thing recommending it: it's totally free, so the number of simulations you run in parallel is bounded by compute availability rather than licenses.

Shameless plug: I'm a cofounder of silogy.io, which offers hosted Verilator and other Verilog sims, plus debugging and collab tools.