[jsheard]

We all knew this was coming, but my question is what's the topology? The same as the regular Pi5, with the RP1 southbridge built-in and only one PCIe lane exposed for the user, or does the CM5 leave off the RP1 and break out all five PCIe lanes for user shenanigans? They have a bare chip supply chain set up from the RP2040, so they could sell the RP1 separately for those who want to integrate it onto their carrier boards.

[jacobmarble]

It looks like the CM5 still has one PCIe lane. https://pip.raspberrypi.com/categories/945-forward-guidance

[ceinewydd]

Be aware that discussing anything in the CM5 Forward Guidance document is tricky, the document still says -

"This whitepaper is restricted and covered by the Raspberry Pi Ltd non-disclosure agreement (NDA). It should not be copied, shared, or duplicated without permission."

[jsheard]

I signed up with a disposable email and got access automatically, it's not that secret evidently. It was probably stricter earlier in development.

[syene]

Good thing nearly none of us here have signed that NDA.