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by busup
786 days ago
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To read a single cache line from DDR4 (basically the same for DDR5 but I'm less familiar) the memory controller needs to: 1. send ACT
2. wait tRCD(RD)
3. send READ
4. wait tCL
5. read the burst from the DQ
The original 10ns number was only taking step 4 into account. tRCDRD is just as long if not longer. Then the burst takes a couple more ns. |
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