[musicale]

I agree. It's a shame that MIPS is mostly dead at this point.

(And a moment of silence for SPARC and OpenSPARC T1/T2 in particular - full 64-bit CPUs that were used in production.)

However, RISC-V shares most of the implementation benefits of MIPS, is unencumbered by IP issues, and seems to be steadily improving in terms of software and hardware support.

[phire]

RISC-V has slightly more complicated instruction formats, but is otherwise feels a lot like a cleaned up and simplified MIPS.

The fact that you can easily see MIPS's 16 bit and (most of) 26 bit immediates in a hex editor is one low-key advantage (for teaching) that MIPS has over RISC-V.

But overall RISC-V is a much better teaching ISA. One great thing about is that there is a core version of the RISC-V spec that only has 47 instructions and essentially nothing else. There is no Memory Paging or Privileged Supervisor mode, and you can skip implementing proper exceptions to make the design even simpler.