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by pjc50 805 days ago
USB is arguably much more complicated than 10base2 internet, which pre-dates it by a long way. In fact, if you're trying to use either PCIe or USB to connect to a 10base2 ethernet network, either of those will be far more work than the Ethernet side.

You might be able to persuade a FTDI-style USB device to bit-bang 10base2 Ethernet for you. You'd implement a "PHY" side which translates the wire traffic to a clean bitstream and aligns the frame start and then just have the PC handle all of it in software for you.
2 comments
yjftsjthsd-h 805 days ago
Oh, good point. I guess it depends on your usecase. I was thinking from the angle of not trusting premade network cards but trusting your USB chips.... which now that you point out, is also not a given. Maybe bare serial (just a wire per tx/rx), but it suddenly occurs to me that I don't know how that's actually connected to the CPU, and I think that approaching this from a security angle is a quick road to madness. OTOH... connecting a microcontroller to serial probably is the simplest option and as an engineering exercise is perfectly reasonable, if not exactly fast, but hey it's not like this was ever going to be performant.
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pjc50 805 days ago
> Maybe bare serial (just a wire per tx/rx), but it suddenly occurs to me that I don't know how that's actually connected to the CPU

In practice today, if you have a DB9 serial port, that goes into the section of the chipset which is concerned with all the "legacy" interfaces, which ultimately turns up on the PCIe bus like everything else.

> I think that approaching this from a security angle is a quick road to madness

Yes.

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15155 805 days ago
USB LS/FS are pretty implementable in select FPGAs and MCUs without a dedicated PHY.
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segfaultbuserr 804 days ago
Ironically, USB SS is more implementable than USB HS without a dedicated PHY. USB SS's PHY is just standard CML differential signaling used for almost all modern high-speed protocols like PCIe or SATA (but with an LFPS extension for link negotiation), most FPGAs already have built-in support for it. Meanwhile USB HS's PHY is a completely non-standard one: it's LVDS-like but the signals are not fully differential, it's half-duplex and needs bus arbitration, etc - only USB HS PHYs speak this odd language.
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