[mnw21cam]

One thing to consider is that the resolution and colour space of your computer's display also depends on available clock speed, so if you reduce that by a factor of 20, you'll also have to reduce the number of pixels in your display by the same factor. So, we'll have worse displays as well as worse compute.

As with all else - just look back to computers about 20 years ago, and that'll give you a good idea of what it'd be like. I guess the main difference is that we might have still been able to miniaturise the transistors in a chip as well as we do now, so you'd still have multi-core computers, which they didn't really do very often 20 years ago.

[throwup238]

Don’t ICs have faster internal PLLs than the advertised clock speed? As long as those signals don’t need to move too far.

They could probably figure out a less efficient parallel bus with lots more leads rather than the pixel, line, and frame sync we have now, at least once we moved on from CRTs (I don’t know how those work wrt phosphors). It’d change the cost tradeoffs and mean more chips nearer the display but not really put us back, as long as other components kept up. I.e. pcie line rate is developing much faster than display size/framerate/bandwidth so limiting factor is the panel development and connection standards.